This repository contains a Verilog implementation of a hard-decision Viterbi decoder for a convolutional code. The design demonstrates how the classical blocks of a Viterbi decoder can be realized in ...

This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The system was designed to be used in conjunction ...

Abstract: Low-density Parity-Check (LDPC) codes have significantly been a vital resource in modern communication systems due to their close-to-capacity error-correcting capabilities and tendency to ...